391 lines
13 KiB
C
391 lines
13 KiB
C
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/**
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**************************************************************************
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* @file at32a423_xmc.h
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* @brief at32a423 xmc header file
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __AT32A423_XMC_H
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#define __AT32A423_XMC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "at32a423.h"
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/** @addtogroup AT32A423_periph_driver
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* @{
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*/
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/** @addtogroup XMC
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* @{
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*/
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/** @defgroup XMC_exported_types
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* @{
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*/
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/**
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* @brief xmc data address bus multiplexing type
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*/
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typedef enum
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{
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XMC_DATA_ADDR_MUX_DISABLE = 0x00000000, /*!< xmc address/data multiplexing disable */
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XMC_DATA_ADDR_MUX_ENABLE = 0x00000002 /*!< xmc address/data multiplexing enable */
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} xmc_data_addr_mux_type;
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/**
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* @brief xmc burst access mode type
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*/
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typedef enum
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{
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XMC_BURST_MODE_DISABLE = 0x00000000, /*!< xmc burst mode disable */
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XMC_BURST_MODE_ENABLE = 0x00000100 /*!< xmc burst mode enable */
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} xmc_burst_access_mode_type;
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/**
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* @brief xmc asynchronous wait type
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*/
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typedef enum
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{
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XMC_ASYN_WAIT_DISABLE = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
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XMC_ASYN_WAIT_ENABLE = 0x00008000 /*!< xmc wait signal during asynchronous transfers enable */
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} xmc_asyn_wait_type;
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/**
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* @brief xmc wrapped mode type
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*/
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typedef enum
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{
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XMC_WRAPPED_MODE_DISABLE = 0x00000000, /*!< xmc direct wrapped burst is disbale */
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XMC_WRAPPED_MODE_ENABLE = 0x00000400 /*!< xmc direct wrapped burst is enable */
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} xmc_wrap_mode_type;
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/**
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* @brief xmc write operation type
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*/
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typedef enum
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{
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XMC_WRITE_OPERATION_DISABLE = 0x00000000, /*!< xmc write operations is disable */
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XMC_WRITE_OPERATION_ENABLE = 0x00001000 /*!< xmc write operations is enable */
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} xmc_write_operation_type;
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/**
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* @brief xmc wait signal type
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*/
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typedef enum
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{
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XMC_WAIT_SIGNAL_DISABLE = 0x00000000, /*!< xmc nwait signal is disable */
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XMC_WAIT_SIGNAL_ENABLE = 0x00002000 /*!< xmc nwait signal is enable */
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} xmc_wait_signal_type;
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/**
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* @brief xmc write burst type
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*/
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typedef enum
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{
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XMC_WRITE_BURST_SYN_DISABLE = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
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XMC_WRITE_BURST_SYN_ENABLE = 0x00080000 /*!< xmc write operations are performed in synchronous mode */
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} xmc_write_burst_type;
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/**
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* @brief xmc extended mode type
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*/
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typedef enum
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{
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XMC_WRITE_TIMING_DISABLE = 0x00000000, /*!< xmc write timing disable */
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XMC_WRITE_TIMING_ENABLE = 0x00004000 /*!< xmc write timing enable */
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} xmc_extended_mode_type;
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/**
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* @brief xmc pccard wait type
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*/
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typedef enum
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{
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XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the pc card/nand flash memory bank disable */
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XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the pc card/nand flash memory bank enable */
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} xmc_nand_pccard_wait_type;
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/**
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* @brief xmc ecc enable type
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*/
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typedef enum
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{
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XMC_ECC_OPERATION_DISABLE = 0x00000000, /*!< xmc ecc module disable */
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XMC_ECC_OPERATION_ENABLE = 0x00000040 /*!< xmc ecc module enable */
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} xmc_ecc_enable_type;
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/**
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* @brief xmc nor/sram subbank type
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*/
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typedef enum
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{
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XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
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XMC_BANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
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XMC_BANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
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XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
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} xmc_nor_sram_subbank_type;
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/**
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* @brief xmc memory type
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*/
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typedef enum
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{
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XMC_DEVICE_SRAM = 0x00000000, /*!< xmc device choice sram */
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XMC_DEVICE_PSRAM = 0x00000004, /*!< xmc device choice psram */
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XMC_DEVICE_NOR = 0x00000008 /*!< xmc device choice nor flash */
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} xmc_memory_type;
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/**
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* @brief xmc data width type
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*/
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typedef enum
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{
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XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
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XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
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} xmc_data_width_type;
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/**
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* @brief xmc wait signal polarity type
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*/
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typedef enum
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{
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XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000, /*!< xmc nwait active low */
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XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200 /*!< xmc nwait active high */
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} xmc_wait_signal_polarity_type;
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/**
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* @brief xmc wait timing type
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*/
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typedef enum
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{
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XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
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XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
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} xmc_wait_timing_type;
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/**
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* @brief xmc access mode type
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*/
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typedef enum
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{
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XMC_ACCESS_MODE_A = 0x00000000, /*!< xmc access mode A */
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XMC_ACCESS_MODE_B = 0x10000000, /*!< xmc access mode B */
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XMC_ACCESS_MODE_C = 0x20000000, /*!< xmc access mode C */
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XMC_ACCESS_MODE_D = 0x30000000 /*!< xmc access mode D */
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} xmc_access_mode_type;
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/**
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* @brief nor/sram banks timing parameters
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*/
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typedef struct
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{
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xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
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xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
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uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
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uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
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uint32_t data_setup_time; /*!< xmc nor/sram data setup time */
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uint32_t bus_latency_time; /*!< xmc nor/sram bus latency time */
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uint32_t clk_psc; /*!< xmc nor/sram clock prescale */
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uint32_t data_latency_time; /*!< xmc nor/sram data latency time */
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xmc_access_mode_type mode; /*!< xmc nor/sram access mode */
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} xmc_norsram_timing_init_type;
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/**
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* @brief xmc nor/sram init structure definition
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*/
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typedef struct
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{
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xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
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xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
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xmc_memory_type device; /*!< xmc nor/sram memory device */
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xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
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xmc_burst_access_mode_type burst_mode_enable; /*!< xmc nor/sram burst mode enable */
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xmc_asyn_wait_type asynwait_enable; /*!< xmc nor/sram nwait in asynchronous transfer enable */
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xmc_wait_signal_polarity_type wait_signal_lv; /*!< xmc nor/sram nwait polarity */
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xmc_wrap_mode_type wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
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xmc_wait_timing_type wait_signal_config; /*!< xmc nor/sram nwait timing configuration */
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xmc_write_operation_type write_enable; /*!< xmc nor/sram write enable */
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xmc_wait_signal_type wait_signal_enable; /*!< xmc nor/sram nwait in synchronous transfer enable */
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xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram read-write timing different */
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xmc_write_burst_type write_burst_syn; /*!< xmc nor/sram memory write mode control */
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} xmc_norsram_init_type;
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typedef struct
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{
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/**
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* @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
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*/
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union
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{
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__IO uint32_t bk1ctrl;
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struct
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{
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__IO uint32_t en : 1; /* [0] */
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__IO uint32_t admuxen : 1; /* [1] */
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__IO uint32_t dev : 2; /* [3:2] */
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__IO uint32_t extmdbw : 2; /* [5:4] */
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__IO uint32_t noren : 1; /* [6] */
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__IO uint32_t reserved1 : 1; /* [7] */
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__IO uint32_t syncben : 1; /* [8] */
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__IO uint32_t nwpol : 1; /* [9] */
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__IO uint32_t wrapen : 1; /* [10] */
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__IO uint32_t nwtcfg : 1; /* [11] */
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__IO uint32_t wen : 1; /* [12] */
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__IO uint32_t nwsen : 1; /* [13] */
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__IO uint32_t rwtd : 1; /* [14] */
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__IO uint32_t nwasen : 1; /* [15] */
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__IO uint32_t crpgs : 3; /* [18:16] */
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__IO uint32_t mwmc : 1; /* [19] */
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__IO uint32_t reserved2 : 12;/* [31:20] */
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} bk1ctrl_bit;
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};
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/**
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* @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1...4
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*/
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union
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{
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__IO uint32_t bk1tmg;
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struct
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{
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__IO uint32_t addrst : 4; /* [3:0] */
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__IO uint32_t addrht : 4; /* [7:4] */
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__IO uint32_t dtst : 8; /* [15:8] */
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__IO uint32_t buslat : 4; /* [19:16] */
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__IO uint32_t clkpsc : 4; /* [23:20] */
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__IO uint32_t dtlat : 4; /* [27:24] */
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__IO uint32_t asyncm : 2; /* [29:28] */
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__IO uint32_t reserved1 : 2; /* [31:30] */
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} bk1tmg_bit;
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};
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} xmc_bank1_ctrl_tmg_reg_type;
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typedef struct
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{
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/**
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* @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
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*/
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union
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{
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__IO uint32_t bk1tmgwr;
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struct
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{
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__IO uint32_t addrst : 4; /* [3:0] */
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__IO uint32_t addrht : 4; /* [7:4] */
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__IO uint32_t dtst : 8; /* [15:8] */
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__IO uint32_t buslat : 4; /* [19:16] */
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__IO uint32_t reserved1 : 8; /* [27:20] */
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__IO uint32_t asyncm : 2; /* [29:28] */
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__IO uint32_t reserved2 : 2; /* [31:30] */
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} bk1tmgwr_bit;
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};
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/**
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* @brief xmc bank1 reserved register
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*/
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__IO uint32_t reserved1;
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} xmc_bank1_tmgwr_reg_type;
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/**
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* @brief xmc bank1 registers
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*/
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typedef struct
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{
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/**
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* @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
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*/
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xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
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/**
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* @brief xmc bank1 reserved register, offset:0x20~0x100
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*/
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__IO uint32_t reserved1[57];
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/**
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* @brief xmc bank1 tmgwr register, offset:0x104~0x11C
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*/
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xmc_bank1_tmgwr_reg_type tmgwr_group[4];
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/**
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* @brief xmc bank1 reserved register, offset:0x120~0x21C
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*/
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__IO uint32_t reserved2[63];
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/**
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* @brief xmc bank1 ext register, offset:0x220~0x22C
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*/
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union
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{
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__IO uint32_t ext[4];
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struct
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{
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__IO uint32_t buslatw2w : 8; /* [7:0] */
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__IO uint32_t buslatr2r : 8; /* [15:8] */
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__IO uint32_t reserved1 : 16;/* [31:16] */
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} ext_bit[4];
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};
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} xmc_bank1_type;
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/**
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* @}
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*/
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#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
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/** @defgroup XMC_exported_functions
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* @{
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*/
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void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
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void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
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void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
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xmc_norsram_timing_init_type* xmc_w_timing_struct);
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void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
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void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
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xmc_norsram_timing_init_type* xmc_w_timing_struct);
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void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
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void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
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||
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||
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/**
|
||
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* @}
|
||
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|
*/
|
||
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||
|
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/**
|
||
|
|
* @}
|
||
|
|
*/
|
||
|
|
|
||
|
|
/**
|
||
|
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* @}
|
||
|
|
*/
|
||
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||
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#ifdef __cplusplus
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||
|
|
}
|
||
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#endif
|
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||
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|
#endif
|