liyuanhong/Frame-rate-optimization
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李远红
2026-04-09 10:14:20 +08:00
commit e325a77b42
584 changed files with 279711 additions and 0 deletions
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112
Bsp/bsp_spi.c Normal file
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#include "bsp_spi.h"
static void gpio_config(void)
{
gpio_init_type gpio_initstructure;
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
gpio_default_para_init(&gpio_initstructure);
/* spi3 sck pin */
gpio_initstructure.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_initstructure.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_initstructure.gpio_mode = GPIO_MODE_MUX;
gpio_initstructure.gpio_pull = GPIO_PULL_DOWN;
gpio_initstructure.gpio_pins = GPIO_PINS_4;
gpio_init(GPIOA, &gpio_initstructure);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE4, GPIO_MUX_5);
gpio_initstructure.gpio_pull = GPIO_PULL_DOWN;
gpio_initstructure.gpio_pins = GPIO_PINS_5;
gpio_init(GPIOA, &gpio_initstructure);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE5, GPIO_MUX_5);
/* spi3 miso pin */
gpio_initstructure.gpio_pull = GPIO_PULL_UP;
gpio_initstructure.gpio_pins = GPIO_PINS_6;
gpio_init(GPIOA, &gpio_initstructure);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE6, GPIO_MUX_5);
/* spi3 mosi pin */
gpio_initstructure.gpio_pull = GPIO_PULL_UP;
gpio_initstructure.gpio_pins = GPIO_PINS_7;
gpio_init(GPIOA, &gpio_initstructure);
gpio_pin_mux_config(GPIOA, GPIO_PINS_SOURCE7, GPIO_MUX_5);
}
static void spi_config(void)
{
spi_init_type spi_init_struct;
/* master spi initialization */
crm_periph_clock_enable(CRM_SPI1_PERIPH_CLOCK, TRUE);
spi_default_para_init(&spi_init_struct);
/* dual line unidirectional full-duplex mode */
spi_init_struct.transmission_mode = SPI_TRANSMIT_FULL_DUPLEX;
spi_init_struct.master_slave_mode = SPI_MODE_SLAVE;
spi_init_struct.mclk_freq_division = SPI_MCLK_DIV_64;
spi_init_struct.first_bit_transmission = SPI_FIRST_BIT_MSB;
spi_init_struct.frame_bit_num = SPI_FRAME_8BIT;
spi_init_struct.clock_polarity = SPI_CLOCK_POLARITY_LOW;
spi_init_struct.clock_phase = SPI_CLOCK_PHASE_1EDGE;
spi_init_struct.cs_mode_selection = SPI_CS_HARDWARE_MODE;
spi_init(SPI1, &spi_init_struct);
spi_i2s_dma_transmitter_enable(SPI1,TRUE);
spi_i2s_dma_receiver_enable(SPI1,TRUE);
spi_enable(SPI1, TRUE);
}
static void dma_config(uint8_t *buffer, uint16_t buffer_size)
{
dma_init_type dma_init_struct;
crm_periph_clock_enable(CRM_DMA2_PERIPH_CLOCK, TRUE);
dmamux_enable(DMA2, TRUE);
dma_reset(DMA2_CHANNEL1);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = buffer_size;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_HIGH;
dma_init_struct.loop_mode_enable = FALSE;
dma_init_struct.memory_base_addr = (uint32_t)buffer;
dma_init_struct.peripheral_base_addr = (uint32_t)&(SPI1->dt);
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
dmamux_init(DMA2MUX_CHANNEL1, DMAMUX_DMAREQ_ID_SPI1_TX);
dma_channel_enable(DMA2_CHANNEL1, TRUE);
dma_reset(DMA2_CHANNEL1);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = buffer_size;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_HIGH;
dma_init_struct.loop_mode_enable = FALSE;
dma_init_struct.memory_base_addr = (uint32_t)buffer;
dma_init_struct.peripheral_base_addr = (uint32_t)&(SPI1->dt);
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init(DMA2_CHANNEL1, &dma_init_struct);
dmamux_init(DMA2MUX_CHANNEL1, DMAMUX_DMAREQ_ID_SPI1_TX);
dma_channel_enable(DMA2_CHANNEL1, TRUE);
}
void spi1_init(uint8_t *buffer, uint16_t buffer_size)
{
gpio_config();
dma_config(buffer, buffer_size);
spi_config();
}