liyuanhong/Frame-rate-optimization
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李远红
2026-04-09 10:14:20 +08:00
commit e325a77b42
584 changed files with 279711 additions and 0 deletions
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Bsp/bsp_uart.c Normal file
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#include "bsp_uart.h"
#include "stdio.h"
#include "string.h"
#if CIRCULAR_BUFFER_ENABLE
#include "circular_buffer.h"
CircBuf_t USART1_RxC = {0};
CircBuf_t USART2_RxC = {0};
CircBuf_t USART3_RxC = {0};
CircBuf_t USART4_RxC = {0};
CircBuf_t USART5_RxC = {0};
CircBuf_t USART1_TxC = {0};
CircBuf_t USART2_TxC = {0};
CircBuf_t USART3_TxC = {0};
CircBuf_t USART4_TxC = {0};
CircBuf_t USART5_TxC = {0};
uint8_t usart1_RX_CBUFF[USART1_RX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart2_RX_CBUFF[USART2_RX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart3_RX_CBUFF[USART3_RX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart4_RX_CBUFF[USART4_RX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart5_RX_CBUFF[USART5_RX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart1_TX_CBUFF[USART1_TX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart2_TX_CBUFF[USART2_TX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart3_TX_CBUFF[USART3_TX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart4_TX_CBUFF[USART4_TX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart5_TX_CBUFF[USART5_TX_BUF_LEN*2]; // ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#endif
uint8_t usart1_tx_buf[USART1_TX_BUF_LEN] = {0};//<2F><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart1_rx_buf[USART1_RX_BUF_LEN] = {0};//<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart3_tx_buf[USART3_TX_BUF_LEN] = {0};//<2F><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart3_rx_buf[USART3_RX_BUF_LEN] = {0};//<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart5_tx_buf[USART5_TX_BUF_LEN] = {0};//<2F><><EFBFBD>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD>
uint8_t usart5_rx_buf[USART5_RX_BUF_LEN] = {0};//<2F><><EFBFBD>ջ<EFBFBD><D5BB><EFBFBD><EFBFBD><EFBFBD>
//<2F><><EFBFBD><EFBFBD>1
void uart1_config(uint32_t band_rate)
{
gpio_init_type gpio_init_struct;
dma_init_type dma_init_struct;
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable( CRM_USART1_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_DMA1_PERIPH_CLOCK, TRUE);
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = BSP_USART1_TX_PIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(USART1_GPIOx, &gpio_init_struct);
gpio_pin_mux_config(USART1_GPIOx, GPIO_PINS_SOURCE9, GPIO_MUX_7);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = BSP_USART1_RX_PIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(USART1_GPIOx, &gpio_init_struct);
gpio_pin_mux_config(USART1_GPIOx, GPIO_PINS_SOURCE10, GPIO_MUX_7);
usart_init(USART1, band_rate, USART_DATA_8BITS, USART_STOP_1_BIT);
usart_transmitter_enable(USART1, TRUE);
usart_receiver_enable(USART1, TRUE);
usart_enable(USART1, TRUE);
nvic_irq_enable(USART1_IRQn, 2, 0);
usart_interrupt_enable(USART1, USART_IDLE_INT, TRUE);
//TX_DMA_init
dma_reset(DMA1_CHANNEL1);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = ARRAYNUM(usart1_tx_buf);
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)&usart1_tx_buf;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART1->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
usart_dma_transmitter_enable(USART1, TRUE);
dmamux_enable(DMA1, TRUE);
dmamux_init(DMA1MUX_CHANNEL1, DMAMUX_DMAREQ_ID_USART1_TX);
//RX_DMA_init
dma_reset(DMA1_CHANNEL2);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = ARRAYNUM(usart1_rx_buf);
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)&usart1_rx_buf;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART1->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL2, &dma_init_struct);
usart_dma_receiver_enable(USART1, TRUE);
dma_channel_enable(DMA1_CHANNEL2,TRUE);
dmamux_enable(DMA1, TRUE);
dmamux_init(DMA1MUX_CHANNEL2, DMAMUX_DMAREQ_ID_USART1_RX);
}
void USART1_IRQHandler(void)
{
uint16_t recv_num = 0;
uint16_t send_num = 0;
//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
if((RESET != usart_interrupt_flag_get(USART1, USART_IDLEF_FLAG)) &&
(RESET != usart_flag_get(USART1, USART_IDLEF_FLAG)))
{
usart_flag_clear(USART1,USART_IDLEF_FLAG);
recv_num = sizeof(usart1_rx_buf) - dma_data_number_get(DMA1_CHANNEL2);
#if CIRCULAR_BUFFER_ENABLE
CircBuf_Push(&USART1_RxC, usart1_rx_buf, recv_num);
#endif
dma_channel_enable(DMA1_CHANNEL2, FALSE);
dma_data_number_set(DMA1_CHANNEL2,sizeof(usart1_rx_buf));
dma_channel_enable(DMA1_CHANNEL2, TRUE);
}
//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
if(RESET != usart_interrupt_flag_get(USART1,USART_TDC_FLAG))
{
#if CIRCULAR_BUFFER_ENABLE
send_num = CircBuf_Pop(&USART1_TxC,usart1_tx_buf,sizeof(usart1_tx_buf));
#endif
if(send_num)
{
dma_channel_enable(DMA1_CHANNEL1,FALSE);
dma_flag_clear(DMA1_FDT1_FLAG);
dma_data_number_set(DMA1_CHANNEL1, send_num);
usart_dma_transmitter_enable(USART1, TRUE);
dma_channel_enable(DMA1_CHANNEL1,TRUE);
}
usart_interrupt_enable(USART1, USART_TDC_INT, FALSE);
}
}
void uart1_dma_send_data(uint8_t *buffer,uint16_t len)
{
dma_channel_enable(DMA1_CHANNEL1,FALSE);
dma_flag_clear(DMA1_FDT1_FLAG);
memcpy(usart1_tx_buf,buffer,len);
dma_data_number_set(DMA1_CHANNEL1, len);
usart_dma_transmitter_enable(USART1, TRUE);
dma_channel_enable(DMA1_CHANNEL1,TRUE);
}
void uart1_init(uint32_t band_rate)
{
uart1_config(band_rate);
#if CIRCULAR_BUFFER_ENABLE
CircBuf_Init(&USART1_RxC, usart1_RX_CBUFF, 1024);
CircBuf_Init(&USART1_TxC, usart1_TX_CBUFF, 1024);
#endif
}
//<2F><><EFBFBD><EFBFBD>3
void uart3_config(uint32_t band_rate)
{
gpio_init_type gpio_init_struct;
dma_init_type dma_init_struct;
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable( CRM_USART3_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_DMA1_PERIPH_CLOCK, TRUE);
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = BSP_USART3_TX_PIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(USART3_GPIOx, &gpio_init_struct);
gpio_pin_mux_config(USART3_GPIOx, GPIO_PINS_SOURCE10, GPIO_MUX_7);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = BSP_USART3_RX_PIN;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(USART3_GPIOx, &gpio_init_struct);
gpio_pin_mux_config(USART3_GPIOx, GPIO_PINS_SOURCE11, GPIO_MUX_7);
usart_init(USART3, band_rate, USART_DATA_8BITS, USART_STOP_1_BIT);
usart_transmitter_enable(USART3, TRUE);
usart_receiver_enable(USART3, TRUE);
usart_enable(USART3, TRUE);
nvic_irq_enable(USART3_IRQn, 2, 0);
usart_interrupt_enable(USART3, USART_IDLE_INT, TRUE);
//TX_DMA_init
dma_reset(DMA1_CHANNEL5);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = ARRAYNUM(usart3_tx_buf);
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)&usart3_tx_buf;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART3->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL5, &dma_init_struct);
usart_dma_transmitter_enable(USART3, TRUE);
dmamux_enable(DMA1, TRUE);
dmamux_init(DMA1MUX_CHANNEL5, DMAMUX_DMAREQ_ID_USART3_TX);
//RX_DMA_init
dma_reset(DMA1_CHANNEL6);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = ARRAYNUM(usart3_rx_buf);
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)&usart3_rx_buf;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART3->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL6, &dma_init_struct);
usart_dma_receiver_enable(USART3, TRUE);
dma_channel_enable(DMA1_CHANNEL6,TRUE);
dmamux_enable(DMA1, TRUE);
dmamux_init(DMA1MUX_CHANNEL6, DMAMUX_DMAREQ_ID_USART3_RX);
}
void USART3_IRQHandler(void)
{
uint16_t recv_num = 0;
uint16_t send_num = 0;
//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
if((RESET != usart_interrupt_flag_get(USART3, USART_IDLEF_FLAG)) &&
(RESET != usart_flag_get(USART3, USART_IDLEF_FLAG)))
{
usart_flag_clear(USART3,USART_IDLEF_FLAG);
recv_num = sizeof(usart3_rx_buf) - dma_data_number_get(DMA1_CHANNEL6);
#if CIRCULAR_BUFFER_ENABLE
CircBuf_Push(&USART3_RxC, usart3_rx_buf, recv_num);
#endif
dma_channel_enable(DMA1_CHANNEL6, FALSE);
dma_data_number_set(DMA1_CHANNEL6,sizeof(usart3_rx_buf));
dma_channel_enable(DMA1_CHANNEL6, TRUE);
}
//<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
if(RESET != usart_interrupt_flag_get(USART3,USART_TDC_FLAG))
{
#if CIRCULAR_BUFFER_ENABLE
send_num = CircBuf_Pop(&USART3_TxC,usart3_tx_buf,sizeof(usart3_tx_buf));
#endif
if(send_num)
{
dma_channel_enable(DMA1_CHANNEL5,FALSE);
dma_flag_clear(DMA1_FDT5_FLAG);
dma_data_number_set(DMA1_CHANNEL5, send_num);
usart_dma_transmitter_enable(USART3, TRUE);
dma_channel_enable(DMA1_CHANNEL5,TRUE);
}
usart_interrupt_enable(USART3, USART_TDC_INT, FALSE);
}
}
void uart3_dma_send_data(uint8_t *buffer,uint16_t len)
{
dma_channel_enable(DMA1_CHANNEL5,FALSE);
dma_flag_clear(DMA1_FDT5_FLAG);
memcpy(usart3_tx_buf,buffer,len);
dma_data_number_set(DMA1_CHANNEL5, len);
usart_dma_transmitter_enable(USART3, TRUE);
dma_channel_enable(DMA1_CHANNEL5,TRUE);
}
void uart3_init(uint32_t band_rate)
{
uart3_config(band_rate);
#if CIRCULAR_BUFFER_ENABLE
CircBuf_Init(&USART3_RxC, usart3_RX_CBUFF, 1024);
CircBuf_Init(&USART3_TxC, usart3_TX_CBUFF, 1024);
#endif
}
//<2F><><EFBFBD><EFBFBD>5
void uart5_config(uint32_t band_rate)
{
gpio_init_type gpio_init_struct;
dma_init_type dma_init_struct;
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable( CRM_USART5_PERIPH_CLOCK, TRUE);
crm_periph_clock_enable(CRM_DMA1_PERIPH_CLOCK, TRUE);
gpio_default_para_init(&gpio_init_struct);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = GPIO_PINS_3;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE3, GPIO_MUX_10);
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
gpio_init_struct.gpio_mode = GPIO_MODE_MUX;
gpio_init_struct.gpio_pins = GPIO_PINS_4;
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
gpio_init(GPIOB, &gpio_init_struct);
gpio_pin_mux_config(GPIOB, GPIO_PINS_SOURCE4, GPIO_MUX_10);
usart_init(USART5, band_rate, USART_DATA_8BITS, USART_STOP_1_BIT);
usart_transmitter_enable(USART5, TRUE);
usart_receiver_enable(USART5, TRUE);
usart_enable(USART5, TRUE);
nvic_irq_enable(USART5_IRQn, 2, 0);
usart_interrupt_enable(USART5, USART_IDLE_INT, TRUE);
//TX_DMA_init
dma_reset(DMA1_CHANNEL1);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = ARRAYNUM(usart5_tx_buf);
dma_init_struct.direction = DMA_DIR_MEMORY_TO_PERIPHERAL;
dma_init_struct.memory_base_addr = (uint32_t)&usart5_tx_buf;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART5->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL1, &dma_init_struct);
usart_dma_transmitter_enable(USART5, TRUE);
dmamux_enable(DMA1, TRUE);
dmamux_init(DMA1MUX_CHANNEL1, DMAMUX_DMAREQ_ID_USART5_TX);
//RX_DMA_init
dma_reset(DMA1_CHANNEL2);
dma_default_para_init(&dma_init_struct);
dma_init_struct.buffer_size = ARRAYNUM(usart5_rx_buf);
dma_init_struct.direction = DMA_DIR_PERIPHERAL_TO_MEMORY;
dma_init_struct.memory_base_addr = (uint32_t)&usart5_rx_buf;
dma_init_struct.memory_data_width = DMA_MEMORY_DATA_WIDTH_BYTE;
dma_init_struct.memory_inc_enable = TRUE;
dma_init_struct.peripheral_base_addr = (uint32_t)&USART5->dt;
dma_init_struct.peripheral_data_width = DMA_PERIPHERAL_DATA_WIDTH_BYTE;
dma_init_struct.peripheral_inc_enable = FALSE;
dma_init_struct.priority = DMA_PRIORITY_MEDIUM;
dma_init_struct.loop_mode_enable = FALSE;
dma_init(DMA1_CHANNEL2, &dma_init_struct);
usart_dma_receiver_enable(USART5, TRUE);
dma_channel_enable(DMA1_CHANNEL2,TRUE);
dmamux_enable(DMA1, TRUE);
dmamux_init(DMA1MUX_CHANNEL2, DMAMUX_DMAREQ_ID_USART5_RX);
}
//void USART5_IRQHandler(void)
//{
// uint16_t recv_num = 0;
// uint16_t send_num = 0;
//
// //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
// if((RESET != usart_interrupt_flag_get(USART5, USART_IDLEF_FLAG)) &&
// (RESET != usart_flag_get(USART5, USART_IDLEF_FLAG)))
// {
// usart_flag_clear(USART5,USART_IDLEF_FLAG);
// recv_num = sizeof(usart5_rx_buf) - dma_data_number_get(DMA1_CHANNEL2);
// #if CIRCULAR_BUFFER_ENABLE
// CircBuf_Push(&USART5_RxC, usart5_rx_buf, recv_num);
// #endif
// dma_channel_enable(DMA1_CHANNEL2, FALSE);
// dma_data_number_set(DMA1_CHANNEL2,sizeof(usart5_rx_buf));
// dma_channel_enable(DMA1_CHANNEL2, TRUE);
// }
//
// //<2F><><EFBFBD><EFBFBD><EFBFBD>ж<EFBFBD>
// if(RESET != usart_interrupt_flag_get(USART5,USART_TDC_FLAG))
// {
// #if CIRCULAR_BUFFER_ENABLE
// send_num = CircBuf_Pop(&USART5_TxC,usart5_tx_buf,sizeof(usart5_tx_buf));
// #endif
// if(send_num)
// {
// dma_channel_enable(DMA1_CHANNEL1,FALSE);
// dma_flag_clear(DMA1_FDT1_FLAG);
// dma_data_number_set(DMA1_CHANNEL1, send_num);
// usart_dma_transmitter_enable(USART5, TRUE);
// dma_channel_enable(DMA1_CHANNEL1,TRUE);
// }
//
// usart_interrupt_enable(USART5, USART_TDC_INT, FALSE);
// }
//}
void usart5_dma_send_data(uint8_t *buffer,uint16_t len)
{
dma_channel_enable(DMA1_CHANNEL1,FALSE);
dma_flag_clear(DMA1_FDT1_FLAG);
memcpy(usart5_tx_buf,buffer,len);
dma_data_number_set(DMA1_CHANNEL1, len);
usart_dma_transmitter_enable(USART5, TRUE);
dma_channel_enable(DMA1_CHANNEL1,TRUE);
}
void uart5_init(uint32_t band_rate)
{
uart5_config(band_rate);
#if CIRCULAR_BUFFER_ENABLE
CircBuf_Init(&USART5_RxC, usart5_RX_CBUFF, 1024);
CircBuf_Init(&USART5_TxC, usart5_TX_CBUFF, 1024);
#endif
}
//ѭ<><D1AD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
#if CIRCULAR_BUFFER_ENABLE
uint8_t usart_tx_push(USART_COM_ID_T com_id, uint8_t *data, uint16_t len)
{
uint16_t ret = 0;
switch (com_id)
{
case USART_1_TR:
ret = CircBuf_Push(&USART1_TxC, data, len);
if(ret > 0)
{
usart_interrupt_enable(USART1,USART_TDC_INT,TRUE);
}
return ret;
case USART_2_TR:
ret = CircBuf_Push(&USART2_TxC, data, len);
if(ret > 0)
{
usart_interrupt_enable(USART2,USART_TDC_INT,TRUE);
}
return ret;
case USART_3_TR:
ret = CircBuf_Push(&USART3_TxC, data, len);
if(ret > 0)
{
usart_interrupt_enable(USART3,USART_TDC_INT,TRUE);
}
return ret;
case USART_4_TR:
ret = CircBuf_Push(&USART4_TxC, data, len);
if(ret > 0)
{
usart_interrupt_enable(USART4,USART_TDC_INT,TRUE);
}
return ret;
case USART_5_TR:
ret = CircBuf_Push(&USART5_TxC, data, len);
if(ret > 0)
{
usart_interrupt_enable(USART5,USART_TDC_INT,TRUE);
}
return ret;
default:
return 0;
}
}
uint8_t usart_rx_recv(USART_COM_ID_T com_id, uint8_t *data, uint16_t len)
{
switch (com_id)
{
case USART_1_TR:
return CircBuf_Pop(&USART1_RxC, data, len);
case USART_2_TR:
return CircBuf_Pop(&USART2_RxC, data, len);
case USART_3_TR:
return CircBuf_Pop(&USART3_RxC, data, len);
case USART_4_TR:
return CircBuf_Pop(&USART4_RxC, data, len);
case USART_5_TR:
return CircBuf_Pop(&USART5_RxC, data, len);
default:
return 0;
}
}
/**
* @brief
* @param[in]
* @return
*/
unsigned int usart_rx_read(USART_COM_ID_T com_id,
uint8_t *data,
uint16_t len)
{
if(data != NULL)
{
switch (com_id)
{
case USART_1_TR:
return CircBuf_Read(&USART1_RxC, data, len);
case USART_2_TR:
return CircBuf_Read(&USART2_RxC, data, len);
case USART_3_TR:
return CircBuf_Read(&USART3_RxC, data, len);
case USART_4_TR:
return CircBuf_Read(&USART4_RxC, data, len);
case USART_5_TR:
return CircBuf_Read(&USART5_RxC, data, len);
default:
return 0;
}
} else {
return 0;
}
}
/**
* @brief
* @param[in]
* @return
*/
unsigned char usart_rx_at(USART_COM_ID_T com_id, uint8_t offset)
{
switch (com_id)
{
case USART_1_TR:
return CircBuf_At(&USART1_RxC, offset);
case USART_2_TR:
return CircBuf_At(&USART2_RxC, offset);
case USART_3_TR:
return CircBuf_At(&USART3_RxC, offset);
case USART_4_TR:
return CircBuf_At(&USART4_RxC, offset);
case USART_5_TR:
return CircBuf_At(&USART5_RxC, offset);
default:
return 0;
}
}
/**
* @brief
* @param[in]
* @return
*/
void usart_rx_drop(USART_COM_ID_T com_id, uint8_t drop_lens)
{
switch (com_id)
{
case USART_1_TR:
CircBuf_Drop(&USART1_RxC, drop_lens);
case USART_2_TR:
CircBuf_Drop(&USART2_RxC, drop_lens);
case USART_3_TR:
CircBuf_Drop(&USART3_RxC, drop_lens);
case USART_4_TR:
CircBuf_Drop(&USART4_RxC, drop_lens);
case USART_5_TR:
CircBuf_Drop(&USART5_RxC, drop_lens);
default:
return;
}
}
int usart_rx_get_rx_data_count(USART_COM_ID_T com_id)
{
switch (com_id)
{
case USART_1_TR:
return CircBuf_GetUsedSize(&USART1_RxC);
case USART_2_TR:
return CircBuf_GetUsedSize(&USART2_RxC);
case USART_3_TR:
return CircBuf_GetUsedSize(&USART3_RxC);
case USART_4_TR:
return CircBuf_GetUsedSize(&USART4_RxC);
case USART_5_TR:
return CircBuf_GetUsedSize(&USART5_RxC);
default:
return 0;
}
}
int usart_rx_probe(USART_COM_ID_T com_id)
{
switch (com_id)
{
case USART_1_TR:
return CircBuf_IsEmpty(&USART1_RxC);
case USART_2_TR:
return CircBuf_IsEmpty(&USART2_RxC);
case USART_3_TR:
return CircBuf_IsEmpty(&USART3_RxC);
case USART_4_TR:
return CircBuf_IsEmpty(&USART4_RxC);
case USART_5_TR:
return CircBuf_IsEmpty(&USART5_RxC);
default:
return 1;
}
}
#endif
int fputc(int ch, FILE *f)
{
while(usart_flag_get(USART3, USART_TDBE_FLAG) == RESET);
usart_data_transmit(USART3, (uint16_t)ch);
while(usart_flag_get(USART3, USART_TDC_FLAG) == RESET);
return ch;
}